The present invention relates generally to packaging for integrated circuits. More particularly, the present invention relates to a structure and process for manufacturing substrate packages for high frequency application.
As substrate packages for integrated circuits on semiconductor chips become denser and faster, there has been a significant increase in the requirements that the substrate packages need to meet. For example the substrate packages designed for microwave applications involve high power density chips and interconnections requiring high currents. This imposes severe restrictions in terms of thermal management and also current carrying capability, on these substrate packages. The substrate packages aimed at applications especially in communications need to be thin and highly brazable. Also, certain electrical design requirements dictate that the backside of the substrate packages be metallized for providing a ground cage and slot line type transmission lines by embedding large area metal features in the dielectric layer. The substrate packages for digital applications require denser wiring and finer features (lines and via holes) to be incorporated at lower costs. It is advantageous if these substrate packages would be available in various coefficient of thermal expansions ranging from 3.times.10.sup.-6 to 18.times.10.sup.-6 C.sup.-1 expanding their application space. There is also a strong drive to reduce the defect density in both the chip carriers and in the passive components in the substrate packages.
The conventional method to build such substrate packages (SCM's and MCM's) utilizes multi-layer-ceramic (MLC) processing. This involves making green sheets from the dielectric powder of choice, screening those green sheets with paste(s) of selected metallization to produce patterns and through sheet connections, or vias, stacking these screened green sheets, laminating the green sheets, and then sintering the green sheets to form a three-dimensionally connected substrate package. Sintering large size substrate packages with the very high metal loading, typically required for the communications packages, creates considerable difficulties in controlling the shrinkage, distortion and flatness of substrate packages at the end of the process. Special processing steps have to be added to assure the flatness of the substrate packages. Also, the backside metallization required to build conventional substrate packages is done by a combination of physical deposition methods and electroplating. The high tolerance required for fabricating substrate packages with very fine features cannot be increased beyond a certain limit due to the distortion of green sheets during various processing steps. Overall processing costs of the substrate packages produced using MLC techniques are relatively higher because of the longer cycle times. Therefore there is a need to develop cost effective ways to produce such substrate packages.